As transistor technology continues to scale and integration density increases, one performance limiter of an IC chip will be heat management and/or removal. Not only does heat affect device operation but it may also affect end user usage patterns. Because transistors and interconnects reliability and performance depend on operating temperatures, cooling electronics and diminishing device hot spots has never been greater. With the continued scaling of device features and increased power density, chip cooling has become increasingly difficult and costly.
One method of continued scaling includes three-dimensional stacking of chips used to form a stacked integrated circuit package. Three-dimensional (3-D) die (e.g., silicon chip die) stacking increases transistor density and chip functionality by vertically integrating two or more dice. 3-D integration also improves interconnect speed by decreasing interconnect wire length, enables smaller system form factor, and reduces power dissipation and crosstalk.
Motivations for three-dimensional (3D) integration include reduction in system size, interconnect delay, power dissipation, and enabling hyper-integration of chips fabricated using disparate process technologies. Although various low-power commercial products implement improved performance and increased device packing density realized by 3D stacking of chips (e.g., using wire bonds), such technologies are not suitable for high-performance chips due to ineffective power delivery and heat removal. For example, high performance chips are projected to dissipate more than 100 W/cm2 and require more than 100 A of supply current. Consequently, when such chips are stacked, challenges in power delivery and cooling become greatly exacerbated.
There exists a need for three dimensional integrated circuits and methods of constructing same including microfluidic interconnects for managing thermal energy created during operation of integrated circuits and also managing power supply noise. It is to the provision of such three dimensional integrated circuits and fabrication methods that the various embodiments of the present invention are directed.